RDRF=0, TDRE=0, TEND=0, MPB=0, ORER=0, FER=0, MPBT=0, PER=0
Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)
| MPBT | Multi-Processor Bit Transfer. Sets the multi-processor bit for adding to the transmission frame 0 (0): Data transmission cycles 1 (1): ID transmission cycles |
| MPB | Multi-Processor Bit. Value of the multi-processor bit in the reception frame 0 (0): Data transmission cycles 1 (1): ID transmission cycles |
| TEND | Transmit End Flag 0 (0): A character is being transmitted. 1 (1): Character transfer has been completed. |
| PER | Parity Error Flag 0 (0): No parity error occurred 1 (1): A parity error has occurred |
| FER | Framing Error Flag 0 (0): No framing error occurred 1 (1): A framing error has occurred |
| ORER | Overrun Error Flag 0 (0): No overrun error occurred 1 (1): An overrun error has occurred |
| RDRF | Receive Data Full Flag 0 (0): No received data is in RDR register 1 (1): Received data is in RDR register |
| TDRE | Transmit Data Empty Flag 0 (0): Transmit data is in TDR register 1 (1): No transmit data is in TDR register |